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VNH50N04
"OMNIFET": FULLY AUTOPROTECTED POWER MOSFET
TARGET DATA TYPE VNH50N04
s s s s s s
V clamp 40 V
R DS(on) 0.012
I lim 50 A
s s
s
s
LINEAR CURRENT LIMITATION THERMAL SHUT DOWN SHORT CIRCUIT PROTECTION INTEGRATED CLAMP LOW CURRENT DRAWN FROM INPUT PIN DIAGNOSTIC FEEDBACK THROUGH INPUT PIN ESD PROTECTION DIRECT ACCESS TO THE GATE OF THE POWER MOSFET (ANALOG DRIVING) COMPATIBLE WITH STANDARD POWER MOSFET STANDARD TO-218 PACKAGE
TO-218
DESCRIPTION The VNH50N04 is a monolithic device made using SGS-THOMSON Vertical Intelligent Power M0 Technology, intended for replacement of standard power MOSFETS in DC to 50 KHz applications. Buit-in thermal shut-down, linear BLOCK DIAGRAM
current limitation and overvoltage clamp protect the chip in harsh enviroments. Fault feedback can be detected by monitoring the voltage at the input pin.
September 1994
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VNH50N04
ABSOLUTE MAXIMUM RATING
Symbol VD S V in ID IR V esd P tot Tj Tc T stg Parameter Drain-source Voltage (V in = 0) Input Voltage Drain Current Reverse DC Output Current Electrostatic Discharge (C= 100 pF, R=1.5 K) Total Dissipation at Tc = 25 C Operating Junction Temperature Case Operating Temperature Storage Temperature
o
Value Internally Clamped 18 Internally Limited -50 2000 208 Internally Limited Internally Limited -55 to 150
Unit V V A A V W
o o o
C C C
THERMAL DATA
R thj-cas e Rthj- amb Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max Max 0.6 30
o o
C/W C/W
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF
Symbol V CLAMP V CLTH V I NC L I DS S I ISS Parameter Drain-source Clamp Voltage Drain-source Clamp Threshold Voltage Input-Source Reverse Clamp Voltage Zero Input Voltage Drain Current (V in = 0) Supply Current from Input Pin I D = 18 A I D = 2 mA I in = -1 mA V DS = 13 V V DS = 25 V V DS = 0 V V in = 8 V 250 Test Conditions V in = 0 V in = 0 Min. 31 30 -1 -0.3 50 200 500 Typ. Max. 45 Unit V V V A A A
ON ()
Symbol VI S(th) R DS( on) Parameter Input Threshold Voltage Static Drain-source On Resistance V DS = V in Test Conditions ID = 1 mA Min. 1 Typ. Max. 3 0.012 TBD Unit V
V in = 10 V I D = 30 A V in = 5 V ID = 30 A
DYNAMIC
Symbol gfs () C oss Parameter Forward Transconductance Output Capacitance Test Conditions V DS = 13 V V DS = 13 V ID = 30 A f = 1 MHz Vin = 0 Min. Typ. 40 1800 3000 Max. Unit S pF
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VNH50N04
ELECTRICAL CHARACTERISTICS (continued) SWITCHING
Symbol t d(on) tr t d(off ) tf t d(on) tr t d(off ) tf t d(on) tr t d(off ) tf (di/dt) on Qg Parameter Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Turn-on Current Slope Total Gate Charge Test Conditions V DD = 15 V V gen = 10 V (see figure 3) V DD = 15 V V gen = 10 V T j = 125 o C (see figure 3) V DD = 15 V V gen = 10 V (see figure 3) V DD = 15 V V in = 10 V V DD = 12 V Id = 30 A Rgen = 10 Min. Typ. 100 200 700 350 100 350 1000 650 1.9 5.7 20 12 TBD V in = 10 V TBD Max. TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Unit ns ns ns ns ns ns ns ns s s s s A/s nC
Id = 30 A Rgen = 10
Id = 30 A Rgen = 1000
ID = 30 A ID = 30 A
SOURCE DRAIN DIODE
Symbol V S D () t rr Q rr I RRM Parameter Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Test Conditions I SD = 30 A V in = 0 Min. Typ. 0.86 TBD TBD TBD Max. TBD Unit V ns C A
I SD = 30 A di/dt = 100 A/s V DD = V T j = 150 o C (see test circuit, figure 5)
PROTECTION
Symbol I lim tdlim T jsh T jrs Igf E as Parameter Drain Current Limit Step Response Current Limit Overtemperature Shutdown Overtemperature Reset Fault Sink Current Single Pulse Avalanche Energy V in = 10 V V DS = 13 V 5 starting T j = 25 o C V DD = 20 V V in = 10 V Rgen = 1 K L = 1.6 mH Test Conditions V in = 10 V V DS = 13 V Min. 35 Typ. 50 40 150 135 50 170 Max. 65 80 190 Unit A s
o
V in = 10 V V D S = 13V
C C
o
mA J
() Pulsed: Pul se duration = 300 s, duty cycle 1.5 %
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VNH50N04
PROTECTION FEATURES During normal operation, the Input pin is electrically connected to the gate of the internal power MOSFET. The device then behaves like a standard power MOSFET and can be used as a switch from DC to 50 KHz. The only difference from the user's standpoint is that a small DC current (Iiss) flows into the Input pin in order to supply the internal circuitry. The device integrates: - OVERVOLTAGE CLAMP PROTECTION: internally set at 42V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads. - LINEAR CURRENT LIMITER CIRCUIT: limits the drain current Id to Ilim whatever the Input pin voltage. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold Tjsh.
-
OVERTEMPERATURE AND SHORT CIRCUIT PROTECTION: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs in the range 150 to 190oC, a typical value being o 170 C. The device is automatically restarted when the chip temperature falls below 135oC. - STATUS FEEDBACK: In the case of an overtemperature fault condition, a Status Feedback is provided through the Input pin. The internal protection circuit disconnects the input from the gate and connects it instead to ground via an equivalent resistance of 200 . The failure can be detected by monitoring the voltage at the Input pin, which will be close to ground potential. Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit (with a small increase in RDS(on)).
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VNH50N04
Fig. 1: Unclamped Inductive Load Test Circuits
Fig. 2: Unclamped Inductive Waveforms
Fig. 3: Switching Times Test Circuits For Resistive Load
Fig. 4: Input Charge Test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
Fig. 6: Waveforms
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VNH50N04
TO-218 (SOT-93) MECHANICAL DATA
mm MIN. A C D E F G H L2 L3 L5 L6 R O - 4 3.95 31 12.2 4.1 - 0.157 0.5 1.1 10.8 14.7 - 18 4.15 0.155 1.220 0.480 0.161 4.7 1.17 2.5 0.78 1.3 11.1 15.2 16.2 0.019 0.043 0.425 0.578 - 0.708 0.163 TYP. MAX. 4.9 1.37 MIN. 0.185 0.046 0.098 0.030 0.051 0.437 0.598 0.637 inch TYP. MAX. 0.193 0.054
DIM.
A
C
L5 L3 L2
L6
D
E H O F R 1 2 3
P025A
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G
VNH50N04
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
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